ADMC328YN datasheet(4/32 Pages) AD

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ADMC328

–4–

REV. B

TIMING PARAMETERS

Parameter

Min

Max

Unit

Clock Signals

Signal tCK is defined as 0.5 tCKIN. The ADMC328 uses an input clock with a

frequency equal to half the instruction rate; a 10 MHz input clock (which is

equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When

tCK values are within the range of 0.5 tCKIN period, they should be substituted for

all relevant timing parameters to obtain specification value.

Example: tCKH = 0.5 tCK – 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.

Timing Requirements:

tCKIN

CLKIN Period

100

150

tCKIL

CLKIN Width Low

tCKIH

CLKIN Width High

Switching Characteristics:

tCKL

CLKOUT Width Low

0.5 tCK – 10

tCKH

CLKOUT Width High

0.5 tCK – 10

tCKOH

CLKIN High to CLKOUT High

Control Signals

Timing Requirement:

tRSP

RESET Width Low

5 tCK

PWM Shutdown Signals

Timing Requirement:

tPWMTPW

PWMTRIP Width Low

tCK

NOTES

1Applies after power-up sequence is complete.

Specifications subject to change without notice.

CLKIN

CLKOUT

tCKL

tCKIL

tCKH

tCKIH

tCKIN

tCKOH

Figure 1. Clock Signals

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