ADMC330BST datasheet(16/20 Pages) AD

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ADMC330

–16–

REV. 0

00000

IMASK

IRQ2

SPORT0 TRANSMIT

SPORT0 RECEIVE

TIMER

IRQ0 OR SPORT1 RECEIVE

IRQ1 OR SPORT1 TRANSMIT

SOFTWARE 0

SOFTWARE 1

1 = ENABLE, 0 = DISABLE

ICNTL

IRQ0 SENSITIVITY

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

1 = EDGE

0 = LEVEL

INTERRUPT NESTING

1 = ENABLE, 0 = DISABLE

IFC

0000

000000

IRQ2

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

SOFTWARE 0

SPORT1 TRANSMIT OR

IRQ1

SPORT1 RECEIVE OR

IRQ0

TIMER

SPORT1 RECEIVE OR

IRQ0

SPORT1 TRANSMIT OR

IRQ1

SOFTWARE 0

SOFTWARE 1

SPORT0 RECEIVE

SPORT0 TRANSMIT

IRQ2

INTERRUPT CLEAR

INTERRUPT FORCE

Figure 11. Interrupt Registers

SYSTEM CONTROLLER OVERVIEW

The System Controller has a number of functions:

1. It decodes the DSP address bus and selects the appropriate

peripheral registers.

2. It controls the ADC multiplexer select lines.

3. It can enable

PWMTRIP and PWMSYNC interrupts.

4. It controls the SPORT0 multiplexer select lines.

5. It resets the peripherals and control registers on hardware,

software or watchdog initiated resets.

6. It handles interrupts generated by the peripherals and

generates a DSP core interrupt signal

IRQ1 (IRQ2).

7. It can be used to control the peripheral test modes.

DSP INTERFACE AND MEMORY MAP

All data transferred between the DSP core and the peripherals is

controlled by the System Controller.

The peripheral registers, with the exception of the ADC read

registers, are right justified, i.e., the LSB of each register is

connected to the LSB of the 16-bit DSP DM data bus DSPD

[15:0]. Any unused MSBs are connected to zeros. The ADMC

peripheral registers are memory mapped to 32 words on the

DSP address space, starting at DSP memory location 0x2000:

1. ADC read registers (0–3)

2. PIO Registers (4–7)

3. PWM Set-Up Registers (8–11)

4. PWM Data Registers (12–15)

5. AUX PWM Data Registers (16, 17)

6. System Registers (21–24)

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