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EVAL-ADM1026EB bảng dữ liệu(PDF) 30 Page - Analog Devices

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Giải thích chi tiết về linh kiện  Complete Thermal and System Management Controller
PDF  56 Pages
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EVAL-ADM1026EB bảng dữ liệu(HTML) 30 Page - Analog Devices

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ADM1026
Rev. A | Page 30 of 56
1 = OUT
OF LIMIT
INT ENABLE
INT CLEAR
INT
INT TEMP
VBAT
AIN8
THERM
AFC
RESERVED
CI
GPIO16
EXT1 TEMP
EXT 2 TEMP
3.3V STBY
3.3V MAIN
+5V
VCCP
+12V
–12V
FAN0
FAN1
FAN2
FAN3
FAN4
FAN5
FAN6
FAN7
FROM FAN SPEED
VALUE AND
LIMIT REGISTERS
1 = OUT
OF LIMIT
VALUE
HIGH LIMIT
GPIO0 TO GPIO7
GPIO8 TO GPIO15
MASKING DATA
FROM SMBus
MASKING DATA
FROM SMBus
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
HIGH LIMIT
LOW LIMIT
VALUE
FROM ANALOG/TEMP
VALUE AND LIMIT
REGISTERS
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
LATCH
RESET
IN
OUT
CI
GPIO16
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK GATING
× 8
STATUS
BIT
MASK
BIT
MASK
REGISTER
1
0
1
2
3
4
5
6
7
MASK
REGISTER
2
0
1
2
3
4
5
6
7
MASK
REGISTER
4
0
1
2
3
4
5
6
7
MASK
REGISTER
3
0
1
2
3
4
5
6
7
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
LATCH
RESET
IN
OUT
MASK REGISTER 5
MASK REGISTER 6
STATUS REGISTER 6
STATUS REGISTER 5
Figure 53. Interrupt Structure



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