REV. 0

AD9848/AD9849

–12–

SERIAL INTERFACE TIMING

SDATA

A0

A1

A2

A4

A5

A6

A7

D0

D1

D2

D3

D4

D5

XX

XX

SCK

SL

A3

NOTES

1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.

2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.

3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.

4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE, OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.

VD

HD

SL UPDATED

VD/HD UPDATED

Figure 3a. Serial Write Operation

SDATA

A0

A1

A2

A4

A5

A6

A7

D0

D1

D2

D3

D4

D5

SCK

SL

A3

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA WORDS.

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA WORD (ALL 6 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE, OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

D0

D1

D2

D3

D4

D5

D0

...

...

...

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

D2

D1

Figure 3b. Continuous Serial Write Operation

COMPLETE REGISTER LISTING

Table I

Register

Description

Register

Description

oprmode

AFE Operation Modes

h1drv

H1 Drive Current

ctlmode

AFE Control Modes

h2drv

H2 Drive Current

preventpdate

Prevents Loading of VD-Updated Registers

h3drv

H3 Drive Current

readback

Enables Serial Register Readback Mode

h4drv

H4 Drive Current

vdhdpol

VD/HD Active Polarity

rgpol

RG Polarity

fieldval

Internal Field Pulse Value

rgposloc

RG Positive Edge Location

hblkretime

Retimes the H1 hblk to Internal Clock

rgnegloc

RG Negative Edge Location

tgcore_rstb

Reset Bar Signal for Internal TG Core

rgdrv

RG Drive Current

h12pol

H1/H2 Polarity Control

shpposloc

SHP Sample Location

h1posloc

H1 Positive Edge Location

shdposloc

SHD Sample Location

h1negloc

H1 Negative Edge Location

Notes on Register Listing:

1. All addresses and default values are expressed in Hexadecimal.

2. All registers are VD/HD updated as shown in Figure 3, except for the above-listed registers that are SL updated.