AD9433SLASHPCB datasheet(10/24 Pages) AD

10 / 24 page

REV. 0

AD9433

–10–

DUTY CYCLE HIGH – %

–60

020

–65

–70

–75

–80

–85

–90

–95

2ND HARMONIC (dBc)

3RD HARMONIC (dBc)

WORST OTHER (dBc)

SNR (dB)

TPC 13. Dynamic Performance vs. Encode Duty Cycle

fS = 105 MSPS, fIN = 49.3 MHz, Differential AIN @ –0.5 dBFS,

SFDR Enabled

–0.75

512

1024

1536

2048

2560

3072

3584

4095

0.25

–0.50

–0.25

0.50

0.75

OUTPUT CODE

TPC 14. Integral Nonlinearity vs. Output Code

with SFDR Disabled

–0.5

512

1024

1536

2048

2560

3072

3584

4095

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

OUTPUT CODE

TPC 15. Differential Nonlinearity vs. Output Code

ENCODE FREQUENCY – MHz

180

ICC (mA)

100

125

200

220

240

260

280

300

IDD (mA)

TPC 16. IDD and ICC vs. Encode Rate. fIN = 10.3 MHz,

Differential AIN @ –0.5 dBFS

–0.75

512

1024

1536

2048

2560

3072

3584

4095

0.25

–0.50

–0.25

0.50

0.75

OUTPUT CODE

TPC 17. Integral Nonlinearity vs. Output Code with

SFDR Enabled

FREQUENCY – MHz

–120

7.68

15.36

23.04

30.72

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

TPC 18. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, 4 WCDMA

Carriers, Differential AIN, SFDR Enabled

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