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AD9218 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD9218 bảng dữ liệu(HTML) 4 Page - Analog Devices |
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4 / 24 page ![]() REV. 0 –4– AD9218–SPECIFICATIONS SWITCHING SPECIFICATIONS Test AD9218BST-40/-65 AD9218BST-80/-105 Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUT PARAMETERS Maximum Encode Rate Full VI 40/65 80/105 MSPS Minimum Encode Rate Full IV 20/20 20/20 MSPS Encode Pulsewidth High (tEH) Full IV 7/6 5/3.8 ns Encode Pulsewidth Low (tEL) Full IV 7/6 5/3.8 ns Aperture Delay (tA)25 °CV 2 2 ns Aperture Uncertainty (Jitter) 25 °C V 3 3 ps rms DIGITAL OUTPUT PARAMETERS Output Valid Time (tV)* Full VI 3 3 ns Output Propagation Delay (tPD)* Full VI 4.5 7 4.5 6 ns Output Rise Time (tR)25 °C V 1 1.0 ns Output Fall Time (tF)25 °C V 1.2 1.2 ns Out of Range Recovery Time 25 °CV 5 5 ns Transient Response Time 25 °CV 5 5 ns Recovery Time from Power-Down 25 °C V 10 10 Cycles Pipeline Delay Full IV 5 5 Cycles NOTES *tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 10% to 90%. Specifications subject to change without notice. SAMPLE N AINA, AINB ENCODE A&B D9A–D0A D9B–D0B DATA N–5 SAMPLE N+1 tPD SAMPLE N+2 SAMPLE N+3 SAMPLE N+4 SAMPLE N+5 SAMPLE N+6 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N tV 1/fS tEL tEH tA Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing (VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.) |
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