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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AD8802AR bảng dữ liệu(PDF) 2 Page - Analog Devices |
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AD8802AR bảng dữ liệu(HTML) 2 Page - Analog Devices |
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2 / 16 page  Parameter Symbol Conditions Min Typ 1 Max Units STATIC ACCURACY Specifications apply to all DACs Resolution N 8 Bits Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ±1/4 +1 LSB Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB Full-Scale Error GFSE –1 1/2 +1 LSB Zero Code Error VZSE –1 1/4 +1 LSB DAC Output Resistance ROUT 35 8 k Ω Output Resistance Match ∆R/R O 1.5 % REFERENCE INPUT Voltage Range 2 VREFH 0VDD V VREFL Pin Available on AD8804 Only 0 VDD V REFH Input Resistance RREFH Digital Inputs = 55H, VREFH = VDD 1.2 k Ω REFL Input Resistance 3 RREFL Digital Inputs = 55H, VREFL = VDD 1.2 k Ω Reference Input Capacitance 3 CREF0 Digital Inputs all Zeros 32 pF CREF1 Digital Inputs all Ones 32 pF DIGITAL INPUTS Logic High VIH VDD = +5 V 2.4 V Logic Low VIL VDD = +5 V 0.8 V Logic High VIH VDD = +3 V 2.1 V Logic Low VIL VDD = +3 V 0.6 V Input Current IIL VIN = 0 V or + 5 V ±1 µA Input Capacitance 3 CIL 5pF POWER SUPPLIES 4 Power Supply Range VDD Range 2.7 5.5 V Supply Current (CMOS) IDD VIH = VDD or VIL = 0 V 0.01 10 µA Supply Current (TTL) IDD VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V 1 4 mA Shutdown Current IREFH SHDN = 0 0.2 10 µA Power Dissipation PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 55 µW Power Supply Sensitivity PSRR VDD = +5 V ± 10% 0.001 0.002 %/% DYNAMIC PERFORMANCE 3 VOUT Settling Time tS ±1/2 LSB Error Band 0.6 µs Crosstalk CT Between Adjacent Outputs 5 50 dB SWITCHING CHARACTERISTICS 3, 6 Input Clock Pulse Width tCH, tCL Clock Level High or Low 15 ns Data Setup Time tDS 5ns Data Hold Time tDH 5ns CS Setup Time tCSS 10 ns CS High Pulse Width tCSW 10 ns Reset Pulse Width tRS 90 ns CLK Rise to CS Rise Hold Time tCSH 20 ns CS Rise to Clock Rise Setup tCS1 10 ns NOTES 1Typicals represent average readings at +25 °C. 2V REFH can be any value between GND and V DD, for the AD8804 VREFL can be any value between GND and VDD. 3Guaranteed by design and not subject to production test. 4Digital Input voltages V IN = 0 V or VDD for CMOS condition. DAC outputs unloaded. P DISS is calculated from (IDD × VDD). 5Measured at a V OUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz). 6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. AD8802/AD8804–SPECIFICATIONS REV. 0 –2– (VDD = +3 V 10% or +5 V 10%, VREFH = +VDD, VREFL = 0 V, –40 C ≤T A ≤ +85 C unless otherwise noted) |
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