EM44DM0888LBA datasheet(5/29 Pages) EOREX

5 / 29 page

EM44DM0888LBA

Feb. 2012

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Pin Description (Simplified)

Name

Function

E8,F8

CK,/CK

(System Clock)

CK and CK are differential clock inputs. All address and control input

signals are sampled on the crossing of the positive edge of CK and

negative edge of CK. Output (read) data is referenced to the crossings

of CK and CK (both directions of crossing).

/CS

(Chip Select)

All commands are masked when CS is registered HIGH. CS provides

for external Rank selection on systems with multiple Ranks. CS is

considered part of the command code.

CKE

(Clock Enable)

CKE high activates and CKE low deactivates internal clock signals and

device input buffers and output drivers. Taking CKE low provides

Precharge Power-Down and Self- Refresh operation (all banks idle), or

Active Power-Down (row Active in any bank). CKE is synchronous for

power down entry and exit and for Self-Refresh entry. CKE is

asynchronous for Self-Refresh exit. CKE must be maintained high

throughout read and write accesses. Input buffers, excluding CK, /CK,

ODT and CKE are disabled during Power Down. Input buffers,

excluding CKE are disabled during Self-Refresh.

H8,H3,H7,J2,

J8,J3,J7,K2,

K8,K3,H2,K7,

L2,L8

A0~A13

(Address)

Provided the row address (RA0 – RA13) for Active commands and the

column address (CA0-CA9) and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the

respective bank. A10 is sampled during a Precharge command to

determine whether the Precharge applies to one bank (A10 LOW) or

all banks (A10 HIGH). If only one bank is to be precharged, the bank is

selected by BA0, BA1 & BA2. The address inputs also provide the

op-code during Mode Register Set commands.

G2,G3,G1

BA0, BA1,BA2

(Bank Address)

BA0 – BA2 define to which bank an Active, Read, Write or Precharge

command is being applied. Bank address also determines if the mode

EMRS cycle.

ODT

(On Die Termination)

ODT (registered HIGH) enables termination resistance internal to the

DDR2 SDRAM. When enabled, ODT is applied to each DQ,

UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will

be ignored if the Extended Mode Register (EMRS(1)) is programmed

to disable ODT.

F7, G7, F3

/RAS,/CAS,/WE

(Command Inputs)

/RAS, /CAS and /WE (along with /CS) define the command being

entered.

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