AD8522

REV. A

–3–

SERIAL INPUT REGISTER DATA FORMAT

Last

First

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

NC

A

B

Sf/Hd

Table I. Truth Table

Data Word

Ext Pins

Sf/Hd

BA

LDA

LDB

DAC Register

Hardware Load:

LX

X

↓↓

Loads DACA + DACB with Data from SR

LX

X

↓

H

Loads DACA with Data from SR

L

XXH

↓

Loads DACB with Data from SR

L

X

X

H

H

No Load

Software Decode Load:

H

L

L

X

X

No Load

HH

L

↓↓

Loads DACB with Data from SR, See Note 1 Below

H

H

L

H

H

No Load

HL

H

↓↓

Loads DACA with Data from SR, See Note 1 Below

H

L

H

H

H

No Load

HH

H

↓↓

Loads DACA + DACB with Data from SR, See 1 Note Below

H

H

H

H

H

No Load

NOTES

3

↓ symbol denotes negative transition.

200µA

1.6 VOLT

SDO

1.6mA

Figure 3. AC Timing SDO Pin Load Circuit

A

B

LD

CS

CLK

SDI

t

CSS

t

LD1

t

LD2

t

CSH

t

CL

t

DS

t

DH

SDI

CLK

LD

RS

t

LDW

t

CLRW

FS

ZS

t

S

±1 LSB

ERROR BAND

t

S

t

LD2

DB11

DB10

Sf/Hd

DB4

DB3

DB2

DB1

DB0

NC

t

LDW

t

CH

SDO

t

PD

Figure 2. Timing Diagram