AD8322 datasheet(3/16 Pages) AD

3 / 16 page

REV. 0

AD8322

–3–

LOGIC INPUTS (TTL/CMOS Compatible Logic)

Parameter

Min

Typ

Max

Unit

Logic “1” Voltage

2.1

5.0

Logic “0” Voltage

0.8

Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN

020

Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN

–600

–100

Logic “1” Current (VINH = 5 V) PD

190

µA

Logic “0” Current (VINL = 0 V) PD

–250

–30

µA

TIMING REQUIREMENTS

Parameter

Min

Typ

Max

Unit

Clock Pulsewidth (TWH)

16.0

Clock Period (TC)

32.0

Setup Time SDATA vs. Clock (TDS)

5.0

Setup Time

DATEN vs. Clock (T

ES)

15.0

Hold Time SDATA vs. Clock (TDH)

5.0

Hold Time

DATEN vs. Clock (T

EH)

3.0

Input Rise and Fall Times, SDATA,

DATEN, Clock (T

R, TF)10

(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)

(

DATEN, CLK, SDATA, PD, V

CC = 5 V: Full Temperature Range)

TES

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

TDS

TEH

8 CLOCK CYCLES

GAIN TRANSFER (G2)

TOFF

TGS

ANALOG

OUTPUT

SIGNAL AMPLITUDE (p-p)

PEDESTAL

CLK

SDATA

DATEN

TON

TWH

VALID DATA WORD G2

Figure 2. Serial Interface Timing

VALID DATA BIT

MSB

MSB-1

MSB-2

TDS

TDH

SDATA

CLK

Figure 3. SDATA Timing

Table I. Gain vs. Gain Code

Decimal

8-Bit SPI Data Word

Gain Code

MSB

LSB

Nominal Gain (dB)

0 0000 001

–12.64

0 0000 010

–6.62

0 0000 100

–0.60

0 0001 000

5.42

0 0010 000

11.44

0 0100 000

17.46

0 1000 000

23.48

128

1 xxxxxxx

29.50

0 = low, 1 = high, x = don’t care.

AD8322 bảng dữ liệu(PDF) 3 Page - Analog Devices

AD8322 bảng dữ liệu(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bảng dữ liệu tải về

Link URL