AD8116-EB datasheet(3/26 Pages) AD

tên linh kiện	AD8116-EB

Giải thích chi tiết về linh kiện	200 MHz, 16 x 16 Buffered Video Crosspoint Switch

PDF	26 Pages

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AD8116

–3–

REV. A

TIMING CHARACTERISTICS

Limit

Parameter

Symbol

Min

Typ

Max

Units

Data Setup Time

CLK Pulsewidth

100

Data Hold Time

CLK Pulse Separation

100

CLK to

UPDATE Delay

0ns

UPDATE Pulsewidth

CLK to DATA OUT Valid

200

Propagation Delay,

UPDATE to Switch On or Off

–

Data Load Time, CLK = 5 MHz

–

µs

CLK,

UPDATE Rise and Fall Times

–

100

RESET Time

–

200

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

DATA IN

CLK

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

OUT15 (D4)

OUT15 (D3)

OUT00 (D0)

TRANSFER DATA FROM SERIAL

LATCHES DURING LOW LEVEL

CLOCK

DATA IN

UPDATE

1 2 3 4 5 6 7 8 9 10

T = 0

INCREASING TIME

Figure 2. Timing Diagram and Programming Example

Table I. Logic Levels

VIH

VIL

VOH

VOL

IIH

IIL

IOH

IOL

CLK, DATA IN,

DATA OUT

CLK, DATA IN,

DATA OUT

CE, UPDATE

2.0 V min

0.8 V max

2.7 V min

0.5 V max

µA max

–400

µA min

–400

µA max

3.0 mA min

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