REV. C

AD8042

–13–

Each of the AD8042’s op amps is configured as a unity gain

creating a totally symmetrical circuit.

If the + input to Amp 2 is grounded and a small positive signal

is applied to the + input of Amp 1, the output of Amp 1 will be

driven to saturation in the positive direction and the input of

Amp 2 driven to saturation in the negative direction. This is

similar to the way a conventional op amp behaves without any

feedback.

+ input of Amp 1, negative feedback is provided which closes

conventional inverting op amp configuration with differential

outputs.

The gain of this circuit from input to either output will be

This gives the circuit the advantage of being able to adjust its

gain by changing a single resistor.

The cable has a characteristic impedance of about 120

W. Each

driver output is back terminated with a pair of 60.4

W resistors

to make the source look like 120

W. The receive end is termi-

nated with 121

W, and the signal is measured differentially with

a pair of scope probes. One channel on the oscilloscope is

inverted and then the signals are added.

The scope photo in Figure 9 shows a 10 MHz, 2 V p-p input signal

driving the circuit with 50 m of category 5 twisted pair wire.

10

0%

100

90

50ns

1V

200mV

200mV

Figure 9. Differential Driver Frequency Response

Single-Supply Differential A/D Driver

The single-ended-to-differential converter circuit is also useful

as a differential driver for video speed, single-ended, differential

input A/D converters. Figure 10 is a schematic that shows such

a circuit differentially driving an AD9220, a 12-bit, 10-MSPS

A/D converter.

AD9220

CAPT

CAPB

SENSE

CML

CLK

19

27

25

14

13

12

11

10

9

8

7

6

5

4

3

2

+5V

0.1 F

REFCOM

16

28

15

26

OTR

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BIT11

BIT12

CLOCK

1

0.1 F

0.1 F

18

17

22

10/16

8

3

2

6

5

7

4

+5V

1

AD8042

2.49k

0.1 F

1k

1k

1k

1k

1k

1k

0.1 F

+5V

+5V

0.1 F

2.49k

0.1 F

0.1 F

+5V

0.1 F

+5V

0.1 F

Figure 10. AD8042 Differential Driver for

the AD9220 12-Bit, 10-MSPS A/D Converter

The circuit was tested with a 1 MHz input signal and clocked at

10 MHz. An FFT response of the digital output is shown in

Figure 11.

Pin 5 is biased at 2.5 V by the voltage divider and bypassed. This

1

4

9

7

2

3

6

8

5

FUND FRQ

1000977

SMPL FRQ 10000000

THD

–82.00

SNR

71.13

SINAD 70.79

SFDR

–86.74

2nd –88.34

3rd –86.74

4th –99.26

5th –90.67

6th –99.47

7th –91.16

8th –97.25

9th –91.61

HARMONICS (dBc)

Figure 11. FFT of AD9220 Output When Driven by AD8042