AD7884/AD7885

REV. C

–12–

The second way is to use the BUSY output of the AD7884 to

generate an interrupt in the MC68000. Because of the nature of

its interrupts, the MC68000 requires additional logic (not

shown in Figure 18) to allow it to be interrupted correctly. For

full information on this, consult the MC68000 User’s Manual.

AD7884 to 80286 Interface

The 80286 is an advanced high performance processor with spe-

cial capabilities aimed at multiuser and multitasking systems.

Figure 19 shows an interface configuration for the AD7884 to

such a system. Note that only signals relevant to the AD7884

are shown. For the full 80286 configuration refer to the iAPX

286 data sheet (Basic System Configuration).

In Figure 19 conversion is started by writing to a selected ad-

dress and causing it CS2 to go low. When conversion is com-

plete, BUSY goes high and initiates an interrupt. The processor

can then read the conversion result.

82288 BUS

CONTROLLER

MRDC

CLK

82284 CLOCK

GENERATOR

CLK

8282 OR

8283

LATCH

8286 OR 8287

TRANSCEIVER

DECODE

CIRCUITRY

CS1

CS2

8259A

INTERRUPT

CONTROLLER

CLK

80286

CPU

D

– D

15

0

A

– A

23

0

AD7884

RD

CS

CONVST

DB15

DB0

BUSY

IR – IR

07

MEMORY READ

Figure 19. AD7884 Interfacing to Basic iAPX 286 System