AD7804 datasheet(4/28 Pages) AD

4 / 28 page

AD7804/AD7805/AD7808/AD7809

REV. A

–4–

(VDD = 3.3 V

10% to 5 V

10%; AGND = DGND = 0 V; Reference =

Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)

Limit at TMIN, TMAX

Parameter

All Versions

Units

Description

100

ns min

CLKIN Cycle Time

ns min

CLKIN High Time

ns min

CLKIN Low Time

ns min

FSIN Setup Time

ns min

Data Setup Time

ns min

Data Hold Time

t6A

ns min

LDAC Hold Time

ns max

FSIN Hold Time

ns min

LDAC, CLR Pulsewidth

100

ns min

LDAC Setup Time

NOTES

1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and

timed from a voltage of (VIL + VIH)/2.

Specifications subject to change without notice.

CLKIN(I)

FSIN(I)

SDIN(I)

DB15

CLR

LDAC1

DB0

1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

LDAC2

Figure 1. Timing Diagram for AD7804 and AD7808

AD7804/AD7808 TIMING CHARACTERISTICS1

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