AD7741YR datasheet(2/12 Pages) AD

2 / 12 page

REV. 0

–2–

AD7741–SPECIFICATIONS

(VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to

TMAX unless otherwise noted.)

B and Y Version

Parameter

Min

Typ

Max

Units

Conditions/Comments

DC PERFORMANCE

Integral Nonlinearity

fCLKIN = 200 kHz

±0.012

% of Span

fCLKIN = 3 MHz

±0.012

% of Span

fCLKIN = 6.144 MHz

±0.024

% of Span

VDD > 4.8 V

Offset Error

±40

Gain Error

+0.8

+1.6

% of Span

Offset Error Drift

±30

µV/°C

Gain Error Drift

±16

ppm of Span/

°C

Power Supply Rejection Ratio

–63

∆V

DD =

±5%

ANALOG INPUT

Input Current

±50

±100

Input Voltage Range

VREF

+2.5 V REFERENCE (REFIN/OUT)

REFIN

Nominal Input Voltage

2.5

Input Impedance

N/A

REFOUT

Output Voltage

2.38

2.50

2.60

Output Impedance

Ω

Reference Drift3

±50

ppm/

°C

Line Rejection

–60

Reference Noise (0.1 Hz to 10 Hz)

100

µV p-p

LOGIC OUTPUT

Output High Voltage, VOH

4.0

Output Sourcing 800

µA7

Output Low Voltage, VOL

0.4

Output Sinking 1.6 mA

Minimum Output Frequency

0.05 fCLKIN

VIN = 0 V

Maximum Output Frequency

0.45 fCLKIN

VIN = VREF

LOGIC INPUT

PD ONLY

Input High Voltage, VIH

2.4

Input Low Voltage, VIL

0.8

Input Current

±100

Pin Capacitance

CLKIN ONLY

Input High Voltage, VIH

3.5

Input Low Voltage, VIL

0.8

Input Current

±2

µA

Pin Capacitance

CLOCK FREQUENCY

Input Frequency

6.144

MHz

For Specified Performance

POWER REQUIREMENTS

VDD

4.75

5.25

IDD (Normal Mode)

Output Unloaded

IDD (Power-Down)

µA

Power-Up Time

µs

Coming Out of Power-Down Mode

NOTES

1Temperature ranges: B Version –40

°C to +85°C: Y Version: –40°C to +105°C.

2See Terminology.

3Guaranteed by design and characterization, not production tested.

4Span = Maximum Output Frequency–Minimum Output Frequency.

5The absolute voltage on the input pin must not go more positive than V

DD – 2.25 V or more negative than GND.

6Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400

µA in order to overdrive the internal reference.

7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.

Specifications subject to change without notice.

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