AD767 datasheet(3/8 Pages) AD

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AD767

REV. A

–3–

ABSOLUTE MAXIMUM RATINGS*

VCC to Power Ground . . . . . . . . . . . . . . . . . . . . .0 V to +18 V

VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V

Digital Inputs (Pins 11, 13–24)

to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V

Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . .

±12 V

Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . .

±12 V

10 V Span R to Reference Ground . . . . . . . . . . . . . . . . .

±12 V

20 V Span R to Reference Ground . . . . . . . . . . . . . . . . .

±24 V

Ref Out, VOUT (Pins 6, 9) . . . Indefinite short to power ground

Momentary Short to VCC

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

TIMING SPECIFICATIONS

(All Models, TA = 25°C, VCC = +12 V or +15 V,

VEE = –12 V or –15 V)

Symbol

Parameter

Min Typ Max

tDS

Data Valid to End of CS

–

(–25

°C to +85°C)

–

(–55

°C to +125°C)

–

tDH

Data Hold Tiıne

–

(–25

°C to +85°C)

–

(–55

°C to +125°C)

–

tCS

Pulse Width

–

(–25

°C to +85°C)

–

(–55

°C to +125°C)

–

tSETT

Output Voltage Settling Time* –

µs

*tSETT is measured referenced to the leading edge of tCS. If tCS > tDS, then

tSETT is measured referenced to the beginning of Data Valid.

PIN CONFIGURATION

PLCC

DIP

ORDERING GUIDE

Linearity

Gain T.C.

Temperature

Error Max

Max

Model

Package

Range CTMIN–TMAX

ppm/ C

AD767JN

Plastic DIP

0 to +70

±1 LSB

AD767JP

PLCC

0 to +70

±1 LSB

AD767KN Plastic DIP

0 to +70

±1/2 LSB

AD767KP

PLCC

0 to +70

±1/2 LSB

AD767AD

Ceramic DIP

–25 to +85

±1 LSB

AD767BD

Ceramic DIP

–25 to +85

±1/2 LSB

AD767SD/

883B

Ceramic DIP

–55 to +125

Note 2

AD767A

Chips

N/A

–25 to +85

±1 LSB

NOTES

1D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.

2For details on grade and package offerings screened in accordance with MIL-STD-883, refer to

the Analog Devices Military Products Databook or current AD767/883B data sheet.

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