PCA9539APW datasheet(5/39 Pages) NXP

5 / 39 page

PCA9539A

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Product data sheet

Rev. 1 — 26 September 2012

5 of 39

NXP Semiconductors

PCA9539A

Low voltage 16-bit I2C-bus I/O port with interrupt and reset

[1]

HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

[2]

Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance

inputs.

[3]

Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance

inputs.

Functional description

Refer to Figure 1 “Block diagram of PCA9539A”.

6.1 Device address

A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1)

or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the

slave address (R/W) defines the operation (read or write) to be performed. A HIGH

(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.

P1_6[3]

I/O

Port 1 input/output 6.

P1_7[3]

I/O

Port 1 input/output 7.

Address input 0. Connect directly to VDD or VSS.

SCL

Serial clock bus. Connect to VDD through a

pull-up resistor.

SDA

I/O

Serial data bus. Connect to VDD through a

pull-up resistor.

VDD

power

Supply voltage.

Table 3.

Pin description …continued

Symbol

Type

Description

TSSOP24

HWQFN24

Fig 4.

PCA9539A device address

R/W

002aah062

hardware

selectable

slave address

fixed

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