AD7244 datasheet(4/12 Pages) AD

4 / 12 page

AD7242/AD7244

REV. A

–4–

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

TIMING CHARACTERISTICS1, 2

Limit at TMIN, TMAX

Parameter

(J, K, A, B Versions)

(S Version)

Units

Conditions/Comments

ns min

TFS

to TCLK Falling Edge

100

ns min

TCLK Falling Edge to TFS

150

200

ns min

TCLK Cycle Time

ns min

Data Valid to TCLK Setup Time

100

ns min

Data Valid to TCLK Hold Time

ns min

LDAC

Pulse Width

NOTES

1Timing specifications are sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-

age level of 1.6 V.

2See Figure 6.

3TCLK Mark/Space ratio is 40/60 to 60/40.

ABSOLUTE MAXIMUM RATINGS*

(TA = +25

°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD

REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

REF INA, REF INB to AGND . . . . . . . –0.3 V to VDD + 0.3 V

Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Operating Temperature Range

J, K Versions

AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

°C to +70°C

AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55

°C to +125°C

(VDD = +5 V

5%, VSS = –5 V

5%, AGND = DGND = 0 V)

PIN CONFIGURATIONS

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300

°C

Power Dissipation (Any Package) to +75

°C . . . . . . . 550 mW

Derates above +75

°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only, functional operation

of the device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

DIP

SOIC

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