AD7010

REV. B

–8–

I Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.8

0.4

0

–0.4

I Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.8

0.4

0

–0.4

Figure 13. AD7010 I vs. Q Waveforms when Transmitting

Random Data

I Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.8

0.4

0

–0.4

Figure 14. AD7010 I vs. Q Waveforms Filtered by an Ideal

Root Raised Cosine Receive Filter

When BIN goes high, the READY signal goes low on the next

rising edge of MCLK and TxCLK becomes active after a further

two MCLK cycles. TxCLK can be used to clock out the trans-

mit data from the ASIC or DSP on the rising edge of TxCLK

and the AD7010 will latch TxDATA on the falling edge of

TxCLK.

When BIN is brought low, the AD7010 will continue to clock in

further eight TxCLK cycles (four symbols). After the final

TxCLK, READY goes high waiting for BIN to be brought high

to begin the next transmit burst.

When Power is brought low, this puts the transmit section into a

low power sleep mode, drawing minimal current. The analog

outputs go high impedance while in low power sleep mode.

A special FTEST (Frequency TEST) mode is provided for the

customer, where no phase modulation takes place and the

modulator outputs remain static. ITx is set to zero and QTx is

set to full scale as Figure 2 illustrates. However, the normal

ramp-up/down envelope is still applied during the beginning and

end of a burst.

These modes are reserved for factory test only and should not be

used by the customer for correct device operation.

I Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.8

0.4

0

–0.4

Figure 15. AD7010 Transmit Constellation Diagram

I Channel – Volts

1.2

–1.2

1.2

0

–0.8

–0.8

–0.4

–1.2

0.8

0.4

0.8

0.4

0

–0.4

Figure 16. AD7010 Constellation Diagram when Filtered

by an Ideal Root Raised Cosine Receive Filter

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

24-Lead SSOP (RS-24)

1. LEAD NO. 1 IDENTIFIED BY A DOT.

2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

0.009 (0.229)

0.005 (0.127)

0.037 (0.94)

0.022 (0.559)

8

°

0

°

0.0256 (0.65)

BSC

0.07 (1.78)

0.066 (1.67)

0.328 (8.33)

0.318 (8.08)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.311 (7.9)

0.301 (7.64)

0.212 (5.38)

0.205 (5.207)

1

24

13

12