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AD6623BC/PCB bảng dữ liệu(PDF) 31 Page - Analog Devices

tên linh kiện AD6623BC/PCB
Giải thích chi tiết về linh kiện  4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
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Trang chủ  http://www.analog.com
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AD6623BC/PCB bảng dữ liệu(HTML) 31 Page - Analog Devices

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REV. 0
AD6623
–31–
Common Function Registers (not associated with a particular channel)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
0x000
7
AD6623 Extension = 0
1
AD6623 Extension = 1
1
6–5
Reserved
No Change
4
Reserved
Wideband Input Disable
3
3
Reserved
Dual Output Enable
3
2
Reserved
No Change
1
Offset Binary Outputs
1
No Change
0
Clip Wideband I/O
3
No Change
0x001
7
First Sync Only
3
No Change
6
Beam on Pin Sync
3
No Change
5
Hop on Pin Sync
3
No Change
4
Start on Pin Sync
3
No Change
3
Ch. D Sync0 Pin Enable
3
No Change
2
Ch. C Sync0 Pin Enable
3
No Change
1
Ch. B Sync0 Pin Enable
3
No Change
0
Ch. A Sync0 Pin Enable
3
No Change
0x002
23–0
Unused
BIST Counter
1, 3
0x003
15–0
Unused
BIST Value (read only)
Channel Function Registers (0x1XX = Ch. A, 0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
0x100
17–16
Unused
Ch. A Start Sync Select3
00: Sync0 (See 0x001)
01: Sync1
10: Sync2
11: Sync3
15–0
Ch. A Start Hold–Off Counter
3
No Change
0x101
7–5
Reserved
No Change
4
Ch. A NCO Amplitude Dither Enable
No Change
3
Ch. A NCO Phase Dither Enable
No Change
2
Ch. A NCO Clear Phase Accumulator on Sync
No Change
1–0
Ch. A NCO Scale
No Change
00: –6 dB
No Change
01: –12 dB
No Change
10: –18 dB
No Change
11: –24 dB
No Change
0x102
31–0
Ch. A NCO Frequency Value3
No Change
0x103
17–16
Unused
Ch. A Hop Sync Select
3
00: Sync0 (See 0x001 Hop)
01: Sync1
10: Sync2
11: Sync3
applied to the Sync pin (Pin 62). See the Synchronization section
for detailed explanations of the different modes.
External Address 4 Sleep
Bits in this register determine how the chip is programmed and
enables the channels. The program bits (D7:D4) must be set high to
allow programming of CMEM and DMEM for each channel.
Sleep bits (D3:D0) are used to activate or sleep channels. These can
be used manually by the user to bring up a channel by simply writing
the required channel high. These bits can also be used in conjunc-
tion with the Start and Sync signals available in External Address
5 to synchronize the channels. See the Synchronization section for a
detailed explanation of different modes.
External Address 3:0 (Data Bytes)
These registers return or accept the data to be accessed for a
read or write to internal addresses
INTERNAL COUNTER REGISTERS AND ON-CHIP RAM
AD6623 and AD6622 Compatibility
The AD6623 functionality is a superset of the AD6622 functionality.
The AD6623 is pin-compatible with AD6622.
AD6622 compatibility is selected when bit 7 of Internal Control
Register 0x000 is low. In this state, all AD6623 extended control
registers are cleared. While in the AD6622 mode the unused
AD6623 pins are three-stated.
Listed below is the mapping of internal AD6623 registers. AD6622
compatibility is selected by setting 0x000:7 low. In this state, all
AD6623 extended control registers are cleared. Registers marked
as “Reserved” must be written low.



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