Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 39 -

Confidential Information

TIMING CHARACTERISTICS

EVBC Interface ASPORT

Parameter

Comment (see Figure 19)

Min

Typ

Max

Units

ASCLK period

384

ns

ASOFS setup time before ASCLK high

20

ns

ASOFS hold time after ASCLK high

20

ns

ASDI setup time before clock low

20

ns

ASDI hold time after clock low

20

ns

ASDO delay after clock high

0

20

ns

ASCLK (O)

ASDI (i)

ASDO (O)

D9

D8

D7

A2

A1

A0

ASOFS (O)

t

71

t

72

t

74

t

75

D9

D8

D7

A2

A1

A0

Figure 19. EVBC Interface ASPORT Timing