AD5532HS datasheet(3/12 Pages) AD

3 / 12 page

REV. 0

–3–

AD5532HS

(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =

DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)

Parameter

1, 2

A Version

Unit

Conditions/Comments

Output Voltage Settling Time

µs max

100 pF, 5 k

Ω Load; Full-Scale Change

Slew Rate

0.85

µs typ

Digital-to-Analog Glitch Impulse

nV-s typ

1 LSB Change around Major Carry

Digital Crosstalk

nV-s typ

Analog Crosstalk

nV-s typ

Digital Feedthrough

0.2

nV-s typ

Output Noise Spectral Density @ 1 kHz

170

nV/

√Hz typ

NOTES

1See Terminology

2Guaranteed by design and characterization, not production tested

3B Version: Industrial temperature range –40

°C to +85°C.

4Timed from the end of a write sequence.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at TMIN, TMAX

Parameter

1, 2, 3

(A Version)

Unit

Conditions/Comments

fUPDATE

1.1

MHz max

Channel Update Rate

fCLKIN

MHz max

SCLK Frequency

ns min

SCLK High Pulsewidth

ns min

SCLK Low Pulsewidth

ns min

SYNC Falling Edge to SCLK Falling Edge Setup Time

ns min

SYNC Low Time

ns min

SYNC High Time

ns min

DIN Setup Time

ns min

DIN Hold Time

280

ns min

19th SCLK Falling Edge to SYNC Falling Edge for Next Write

ns min

RESET Pulsewidth

NOTES

1See Timing Diagrams in Figure 1.

2Guaranteed by design and characterization, not production tested.

3All input signals are specified with t

R = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

AC CHARACTERISTICS

(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

AGND = DGND = DAC_GND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)

LSB

MSB

SCLK

SYNC

DIN

RESET

Figure 1. Serial Interface Timing Diagram

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