AD549

REV. A

–7–

mized. Input capacitance can substantially degrade signal band-

width and the stability of the I-to-V converter. The case of the

AD549 is connected to Pin 8 so that it can be bootstrapped

near the input potential. This minimizes pin leakage and input

common-mode capacitance due to the case. Guard schemes for

inverting and noninverting amplifier topologies are illustrated in

Figures 28 and 29.

Figure 28. Inverting Amplifier with Guard

Figure 29. Noninverting Amplifier with Guard

Other guidelines include keeping the circuit layout as compact

as possible and input lines short. Keeping the assembly rigid

and minimizing sources of vibration will reduce triboelectric and

piezoelectric effects. All precision high impedance circuitry re-

quires shielding against interference noise. Low noise coax or

triax cables should be used for remote connections to the input

signal lines.

OFFSET NULLING

The AD549’s input offset voltage can be nulled by using balance

Pins 1 and 5, as shown in Figure 30. Nulling the input offset

voltage in this fashion will introduce an added input offset volt-

age drift component of 2.4

µV/°C per millivolt of nulled offset

(a maximum additional drift of 0.6

µV/°C for the AD549K,

1.2

µV/°C for the AD549L, 2.4 µV/°C for the AD549J).

Figure 30. Standard Offset Null Circuit

The approach in Figure 31 can be used when the amplifier is

used as an inverter. This method introduces a small voltage

referenced to the power supplies in series with the amplifier’s

does not have high enough insulation resistance. Therefore, the

AD549’s input leads should be connected to standoffs made of

insulating material with adequate volume resistivity (e.g.,

Teflon*). The surface of the insulator’s surface must be kept

clean in order to preserve surface resistivity. For Teflon, an ef-

fective cleaning procedure consists of swabbing the surface with

high-grade isopropyl alcohol, rinsing with deionized water, and

baking the board at 80

°C for 10 minutes.

Figure 26. Sources of Parasitic Leakage Currents

In addition to high volume and surface resistivity, other proper-

ties are desirable in the insulating material chosen. Resistance to

water absorption is important since surface water films drasti-

cally reduce surface resistivity. The insulator chosen should also

exhibit minimal piezoelectric effects (charge emission due to

mechanical stress) and triboelectric effects (charge generated by

friction). Charge imbalances generated by these mechanisms can

appear as parasitic leakage currents. These effects are modeled

lists various insulators and their properties.

1

Volume

Minimal

Minimal

Resistance

Resistivity

Triboelectric

Piezoelectric to Water

Material

( –CM)

Effects

Effects

Absorption

Teflon*

WW

G

Kel-F**

WM

G

Sapphire

MG

G

Polyethylene

MG

M

Polystyrene

WM

M

Ceramic

WM

W

Glass Epoxy

WM

W

PVC

GM

G

Phenolic

WG

W

G–Good with Regard to Property

M–Moderate with Regard to Property

W–Weak with Regard to Property

Figure 27. Insulating Materials and Characteristics

Guarding the input lines by completely surrounding them with a

metal conductor biased near the input lines’ potential has two

major benefits. First, parasitic leakage from the signal line is

reduced since the voltage between the input line and the guard

is very low. Second, stray capacitance at the input node is mini-

Ohio, 1977.

*Teflon is a registered trademark of E.I. DuPont Co.

**Kel-F is a registered trademark of 3-M Company.