AD9525 datasheet(39/48 Pages) AD

39 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 39 of 48

Table 36. Reserved

Reg.

Addr.

(Hex)

Bits

Bit Name

Description

0x01B

[7:0]

Reserved

Reserved.

0: default. All bits should be set to 0.

Table 37. PLL Block Power-Down

Reg.

Addr.

(Hex)

Bits

Name

Description

0x01C 7

N divider

ECL 2 CMOS

power-down

Turns off the N divider’s output clock. This stops the clock to the PFD and the frequency monitors.

0: clock on (default).

1: clock off.

N divider

power-down

N divider power-down.

0: N divider on (default).

1: N divider off.

REFB Divider

ECL 2 CMOS

power-down

This bit stops the clock to the frequency monitors for REFB. If this bit is disabled, the automatic reference

switchover does not operate. In some configurations, enabling the REFB divider ECL 2 CMOS may increase

reference spurs on clock outputs.

0: on.

1: off (default).

REFA Divider

ECL 2 CMOS

power-down

This bit stops the clock to the frequency monitors for REFA. If this bit is disabled, the automatic reference

switchover does not operate. In some configurations, enabling the REFA Divider ECL 2 CMOS may

increase reference spurs on clock outputs.

0: on (default).

1: off.

REFB divider

power-down

Powers down REFB divider. The REFB input receiver is still powered up.

0: REFB divider on (default).

1: REFB divider off.

REFA divider

power-down

Powers down REFA divider. The REFA input receiver is still powered up.

0: REFA divider on (default).

1: REFA divider off.

REFB channel

power-down

Powers down REFB channel. The REFB input receiver is powered down.

0: REFB channel on.

1: REFB channel off (default).

REFA channel

power-down

Powers down REFA channel. The REFA input receiver is powered down.

0: REFA channel on (default).

1: REFA channel off.

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