AWC6340P9 datasheet(5/10 Pages) ANADIGICS

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PRELIMINARY DATA SHEET - Rev 1.8

02/2012

AWC6340

APPLICATION

POUT

LEVELS

BIAS

MODE

VEN

VMODE

VCC

VBATT

Low power

≤

+15 dBm

Low+1.8 V+1.8 V3.1 - 4.35 V> 3.1 V

High power> +15 dBmHigh+1.8 V0 V3.1 - 4.35 V> 3.1 V

Shutdown-

Shutdown

0 V0 V3.1 - 4.35 V> 3.1 V

APPLICATION INFORMATION

Table 5: Bias Control

To ensure proper performance, refer to all related

Application Notes on the ANADIGICS web site:

http://www.anadigics.com

Shutdown Mode

The power amplifier may be placed in a shutdown

mode by applying logic low levels (see Operating

Ranges table) to the VEN and VMODE voltages.

Bias Modes

The power amplifier may be placed in either Low or

High Bias modes by applying the appropriate logic

level (see Operating Ranges table) to the VMODE pin.

The Bias Control table below lists the recommended

modes of operation for various applications.

Two operating modes are recommended to optimize

current consumption. High Bias/High Power operating

mode is for POUT levels > 15 dBm. At about 15 dBm,

the PAshould be “Mode Switched” to Low Power Mode.

VEN

VCC

note 1

RFIN

notes 1,2

OFF Sequence

Referenced After 90% of Rise

Time

Referenced Before10% of Fall

Time

ON Sequence

On Sequence Start

T_0N=0µ

T_0N+1µS

T_0N+3µS

Off Sequence Start

T_0FF= 0µ

T_0FF+2µST_0FF+3µS

Vcontrols

Venable/Vmode(s)

Rise/Fall Max 1

µS

Defined at 10% to 90%

of Min/Max Voltage

Figure 3: Recommended ON/OFF Timing Sequence

Notes:

(1) Level might be changed after RF is ON.

(2) RF OFF defined as PIN ≤ -30 dBm.

(3) Switching simultaneously between VMODE and VEN is not recommended.

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