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AD5322 bảng dữ liệu(PDF) 3 Page - Analog Devices

tên linh kiện AD5322
Giải thích chi tiết về linh kiện  2.5 V to 5.5 V, 230 uA Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs
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Trang chủ  http://www.analog.com
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AD5322 bảng dữ liệu(HTML) 3 Page - Analog Devices

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REV. 0
–3–
AD5302/AD5312/AD5322
AC CHARACTERISTICS
1 (VDD = +2.5 V to +5.5 V; RL = 2 k
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
otherwise noted.)
B Version
3
Parameter
2
Min
Typ
Max
Units
Conditions/Comments
Output Voltage Settling Time
VREF = VDD = +5 V
AD5302
6
8
µs
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5312
7
9
µs
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5322
8
10
µs
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate
0.7
V/
µs
Major-Code Transition Glitch Energy
12
nV-s
1 LSB Change Around Major Carry (011 . . . 11 to 100 . . . 00)
Digital Feedthrough
0.10
nV-s
Analog Crosstalk
0.01
nV-s
DAC-to-DAC Crosstalk
0.01
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
Total Harmonic Distortion
–70
dB
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1Guaranteed by design and characterization, not production tested.
2See Terminology.
3Temperature range: B Version: –40
°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
t1
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
13
ns min
SCLK Low Time
t4
0
ns min
SYNC to SCLK Active Edge Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t8
100
ns min
Minimum
SYNC High Time
t9
20
ns min
LDAC Pulsewidth
t10
20
ns min
SCLK Falling Edge to
LDAC Rising Edge
NOTES
1Guaranteed by design and characterization, not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of (VIL + VIH)/2.
3See Figure 1.
Specifications subject to change without notice.
(VDD = +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
SCLK
SYNC
DIN*
t2
t3
t5
t6
t7
t4
DB15
t1
DB0
t9
t10
LDAC
LDAC
*SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER
t8
Figure 1. Serial Interface Timing Diagram



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