AD5301 datasheet(3/15 Pages) AD

3 / 15 page

REV. 0

AD5301/AD5311/AD5321

–3–

AC CHARACTERISTICS1

B Version3

Parameter2

Min

Typ

Max

Units

Conditions/Comments

Output Voltage Settling Time

VDD = +5 V

AD5301

µs

1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)

AD5311

µs

1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)

AD5321

µs

1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)

Slew Rate

0.7

µs

Major-Code Change Glitch Impulse

nV-s

1 LSB Change Around Major Carry

Digital Feedthrough

0.3

nV-s

NOTES

1See Terminology

2Guaranteed by design and characterization, not production tested.

3Temperature ranges are as follows: B Version: –40

°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1

Limit at TMIN, TMAX

Parameter2

(B Version)

Units

Conditions/Comments

fSCL

400

kHz max

SCL Clock Frequency

2.5

µs min

SCL Cycle Time

0.6

µs min

tHIGH, SCL High Time

1.3

µs min

tLOW, SCL Low Time

0.6

µs min

tHD,STA, Start/Repeated Start Condition Hold Time

100

ns min

tSU,DAT, Data Setup Time

0.9

µs max

tHD,DAT, Data Hold Time

µs min

0.6

µs min

tSU,STA, Setup Time for Repeated Start

0.6

µs min

tSU,STO, Stop Condition Setup Time

1.3

µs min

tBUF, Bus Free Time Between a STOP Condition and a START Condition

t10

300

ns max

tR, Rise Time of Both SCL and SDA when Receiving

ns min

May be CMOS Driven

t11

250

ns max

tF, Fall Time of SDA when Receiving

300

ns max

tF, Fall Time of Both SCL and SDA when Transmitting

20 + 0.1Cb

ns min

400

pF max

Capacitive Load for Each Bus Line

NOTES

1See Figure 1.

2Guaranteed by design and characterization, not production tested.

3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

IH MIN of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

b is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Specifications subject to change without notice.

(VDD = +2.5 V to +5.5 V; RL = 2 k

Ω to GND; C

L = 200 pF to GND; All specifications TMIN to TMAX unless

otherwise noted.)

(VDD = +2.5 V to +5.5 V. All specifications TMIN to TMAX unless otherwise noted.)

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