AD2S93AP datasheet(3/12 Pages) AD

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AD2S93

REV. A

–3–

Parameter

Test Conditions

Min

Typ

Max

Units

SERIAL CLOCK (SCLK)

SCK Input Rate

MHz

Maximum Read Rate (16 Bits)

Continuous

9.2

µs

POWER SUPPLY

5710

NOTES

1The signal input voltage maximum should always be set at 10% less than the reference input.

2Nominal + FS = V

A–B = VREF/2, FS = –VA–B = VREF/2

3With G = 10; Sensitivity 34.2

µV pk/LSB

4Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.”

Specifications subject to change without notice.

SCLK

DATA

LSB

MSB

t * = THE MINIMUM ACCESS TIME: USER DEPENDENT

TOTAL MAX READ TIME =

2 + 16. (t3 + t4 ) + t7

TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns

TOTAL MAX READ TIME = 600 + 8000 + 150 ns

TOTAL MAX READ TIME = 8.750 µs (SINGLE READ ONLY)

Timing Diagram

Parameter

AD2S93

Units

Test Conditions

150

ns max

to DATA Enable

600

ns min

to 1st SCLK Positive Edge

250

ns min

SCLK High Pulse

250

ns min

SCLK Low Pulse

100

ns max

SCLK Positive Edge to DATA Valid

600

ns min

High Pulse Width

150

ns max

High to DATA High Z (Bus Relinquish)

NOTE

1SCLK can only be applied after t

2 has elapsed.

TIMING CHARACTERISTICS (V

DD = +5 V

± 5%, AGND = DGND = 0 V, T

A = –40

°C to +85°C unless otherwise noted)

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