REV. 0

AD1887

–13–

Extended Audio ID Register (Index 28h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

8

2h

8

2 h

8

2 h

8

2h

8

2D

I

o

i

d

u

A

d

e

d

n

e

t

x

ED

I

o

i

d

u

A

d

e

d

n

e

t

x

E

D

I

o

i

d

u

A

d

e

d

n

e

t

x

E

D

I

o

i

d

u

A

d

e

d

n

e

t

x

ED

I

o

i

d

u

A

d

e

d

n

e

t

x

E1

D

I1

D

I

1

D

I

1

D

I1

D

I0

D

I0

D

I

0

D

I

0

D

I0

D

IX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XA

R

VA

R

V

A

R

V

A

R

VA

R

Vh

1

0

0

0h

1

0

0

0

h

1

0

0

0

h

1

0

0

0h

1

0

0

0

Note: The Extended Audio ID is a read only register.

VRA

Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.

ID[1:0]

ID1, ID0 is a 2-bit field which indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.

Extended Audio Status and Control Register (Index 2Ah)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

A

2h

A

2

h

A

2

h

A

2h

A

2l

r

t

C

/

t

a

t

S

o

i

d

u

A

d

'

t

x

El

r

t

C

/

t

a

t

S

o

i

d

u

A

d

'

t

x

E

l

r

t

C

/

t

a

t

S

o

i

d

u

A

d

'

t

x

E

l

r

t

C

/

t

a

t

S

o

i

d

u

A

d

'

t

x

El

r

t

C

/

t

a

t

S

o

i

d

u

A

d

'

t

x

EX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XA

R

VA

R

V

A

R

V

A

R

VA

R

Vh

0

0

0

0h

0

0

0

0

h

0

0

0

0

h

0

0

0

0h

0

0

0

0

Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio

features.

VRA

Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio mode (sample rate control registers and

SLOTREQ signaling).

PCM DAC Rate Register (Index 2Ch)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S

9

R

S

9

R

S9

R

S8

R

S8

R

S

8

R

S

8

R

S8

R

S7

R

S7

R

S

7

R

S

7

R

S7

R

S6

R

S6

R

S

6

R

S

6

R

S6

R

S5

R

S5

R

S

5

R

S

5

R

S5

R

S4

R

S4

R

S

4

R

S

4

R

S4

R

S3

R

S3

R

S

3

R

S

3

R

S3

R

S2

R

S2

R

S

2

R

S

2

R

S2

R

S1

R

S1

R

S

1

R

S

1

R

S1

R

S0

R

S0

R

S

0

R

S

0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both

sample rates are reset to 48 kHz.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in

1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the

codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when

read, otherwise the closest rate supported is returned.

PCM ADC Rate Register (Index 32h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S

9

R

S

9

R

S9

R

S8

R

S8

R

S

8

R

S

8

R

S8

R

S7

R

S7

R

S

7

R

S

7

R

S7

R

S6

R

S6

R

S

6

R

S

6

R

S6

R

S5

R

S5

R

S

5

R

S

5

R

S5

R

S4

R

S4

R

S

4

R

S

4

R

S4

R

S3

R

S3

R

S

3

R

S

3

R

S3

R

S2

R

S2

R

S

2

R

S

2

R

S2

R

S1

R

S1

R

S

1

R

S

1

R

S1

R

S0

R

S0

R

S

0

R

S

0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both

sample rates are reset to 48 kHz.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in

1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the

codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when

read, otherwise the closest rate supported is returned.