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AD1855 bảng dữ liệu(PDF) 2 Page - Analog Devices

tên linh kiện AD1855
Giải thích chi tiết về linh kiện  Stereo, 96 kHz, Multibit DAC
PDF  15 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD1855 bảng dữ liệu(HTML) 2 Page - Analog Devices

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–2–
REV. B
AD1855–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)
+5.0 V
Ambient Temperature
+25
°C
Input Clock
24.576 MHz (512
× F
S Mode)
Input Signal
1.0013 kHz
–0.5 dB Full Scale
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
20 Bits
Load Impedance
6 k
Ω
Input Voltage HI
4.0 V
Input Voltage LO
0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
Min
Typ
Max
Units
Resolution
20
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
110
dB
With A-Weighted Filter
108
113
dB
Total Harmonic Distortion + Noise
–97
–91
dB
0.0014
%
Analog Outputs
Differential Output Range (
±Full Scale)
5.6
V p-p
Output Impedance at Each Output Pin
200
Ω
Output Capacitance at Each Output Pin
20
pF
CMOUT
2.5
V
Gain Error
–5.0
±3.0
+5.0
%
Interchannel Gain Mismatch
–0.15
+0.15
dB
Gain Drift
150
300
ppm/
°C
Interchannel Crosstalk (EIAJ Method)
–120
dB
Interchannel Phase Deviation
±0.1
Degrees
Mute Attenuation
–120
dB
De-Emphasis Gain Error
±0.1
dB
DIGITAL TIMING (Guaranteed over 0 C to +70 C, AVDD = DVDD = +5.0 V
10%)
Min
Max
Units
tDMP
MCLK Period (512 FS Mode)
35
ns
tDMP
MCLK Period (384 FS Mode)
48
ns
tDMP
MCLK Period (256 FS Mode)
70
ns
tDML
MCLK LO Pulsewidth (All Mode)
0.4
× t
DMP
ns
tDMH
MCLK HI Pulsewidth (All Mode)
0.4
× tDMP
ns
tDBH
BCLK HI Pulsewidth
20
ns
tDBL
BCLK LO Pulsewidth
20
ns
tDBP
BCLK Period
140
ns
tDLS
L
RCLK Setup
20
ns
tDLH
L
RCLK Hold (DSP Serial Port Mode Only)
5
ns
tDDS
SDATA Setup
5
ns
tDDH
SDATA Hold
10
ns
tPDRP
PD/RST LO Pulsewidth
4 MCLK Periods
ns



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