AS-Interface Slave IC

AS2701A (ISA3+)

Rev. C, October 2000

Page 5 of 16

Write Cycle

After the device address, the write cycle R/W-Bit=0, necessary for the identification of the write

cycle, is sent. The E

Then the data byte which should be written into the E

signal of the E

Read Cycle

The read cycle is similar to the herein described write cycle. In this case the R/W-Bit = 1 which

causes the E

acknowledge.

START

Condition

STOP

Condition

SDA

SCL

The START condition is recognized by the E

SDA during the high phase of the clock.

The STOP condition is present when a L/H edge arises on the dataline SDA during the high

phase of the clock SCL. The timing of the E

quartz frequency of 5.333 MHz.