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AT91SAM bảng dữ liệu(PDF) 22 Page - ATMEL Corporation |
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AT91SAM bảng dữ liệu(HTML) 22 Page - ATMEL Corporation |
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22 / 67 page ![]() 22 11100BS–ATARM–31-Jul-12 SAM4S Series [Preliminary] Entering Backup mode: • Set the SLEEPDEEP bit of Cortex_M4 to 1 • Set the VROFF bit of SUPC_CR to 1 Exit from Backup mode happens if one of the following enable wake up events occurs: • WKUPEN0-15 pins (level transition, configurable debouncing) • Supply Monitor alarm •RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 32 µA (total current consumption) if the internal voltage regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered by setting WAITMODE bit to 1 (in PMC clock generator Main Oscillator register) with LPM = 1 (Low Power Mode bit in PMC_FSMR) and with FLPM = 00 or FLPM=01 (Flash Low Power Mode bits in PMC_FSMR). The Cortex-M4 is able to handle external events or internal events in order to wake-up the core. This is done by configuring the external lines WUP0-15 as fast startup wake-up pins (refer to Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU. Entering Wait Mode: • Select the 4/8/12 MHz fast RC oscillator as Main Clock • Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) • Set the FLPM bitfield in the PMC Fast Startup Mode Register (PMC_FSMR) • Set Flash Wait State at 0. • Set the WAITMODE bit = 1 in PMC Main Oscillator Register (CKGR_MOR) • Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR) Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions. Depending on Flash Low Power Mode (FLPM) value, the Flash will enter in three different modes: • FLPM[00] in Standby mode • FLPM[01] in Deep Power Down mode • FLPM[10] in mode Idle. Following the Flash mode selection, the consumption in wait mode will decrease. In Deep Power Down mode the recovery time of the Flash in Standby mode will be less than the power up delay. |
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