PXR40 Product Brief, Rev. 1

Preliminary—Subject to Change Without Notice

Features

Freescale Semiconductor

16

2.5.16

Power management unit (PMU)

The PXR40’s power management unit includes the following features:

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Externally 5 V is required with the 3.3 V being supplied by an internal regulator running off the

5 V supply

— Can also supply 3.3 V externally

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On-chip regulator controller supplies the 1.2 V via external components

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All supply voltages have voltage monitors and both the VDD regulator and all monitors except

•

The chip uses a protected POR strategy, that is, the chip is guaranteed to run at the voltage point

that RESET is released

2.5.17

Interrupt controller (INTC)

The PXR40 implements an interrupt controller that features the following:

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Priority-based preemptive scheduling of interrupt service requests (ISRs), suitable for statically

scheduled hard real-time systems

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448 software-configurable interrupt sources

— Can be used to break the work involved in servicing an interrupt request into a high priority

portion and a low priority portion:

High priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a

software-configurable interrupt request to finish the servicing in a lower priority ISR.

Therefore these software-configurable interrupt requests can be used instead of the peripheral

ISR scheduling a task through the RTOS.

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16 priority levels so that lower priority ISRs do not delay the execution of higher priority ISRs

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Software-configurable priorities of ISR or tasks

— Modifying the priority can be used to implement the priority ceiling protocol for accessing

shared resources

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For high priority interrupt requests, minimized time from the assertion of the interrupt request from

the peripheral to when the processor is executing the interrupt service routine (ISR)

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A unique vector for each interrupt request source for quick determination of which ISR needs to

be executed

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Support for a critical or non maskable interrupt

— Non-maskable interrupt (NMI) multiplexed on WKPCFG pin to allow connection to the

critical or non maskable input of the CPU core, bypassing the interrupt controller and all

multiplexing and selection logic (provides an interrupt request to the core that is higher priority

than any other interrupting source in the device)