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WM8985GEFL/R bảng dữ liệu(PDF) 86 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R bảng dữ liệu(HTML) 86 Page - Wolfson Microelectronics plc |
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86 / 121 page ![]() WM8985 Production Data w PD, Rev 4.6, July 2009 86 GENERAL PURPOSE INPUT/OUTPUT The WM8985 has three dual purpose input/output pins. • CSB/GPIO1: CSB / GPIO1 pin • L2/GPIO2: Left channel line input / headphone detection input • R2/GPIO3: Right channel line input / headphone detection input The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 function is provided for use as jack detection input or general purpose output. The default configuration for the CSB/GPIO1 is to be an input. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. Table 45 illustrates the functionality of the GPIO1 pin when used as a general purpose output. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 (08h) GPIO Control 2:0 GPIO1SEL 000 CSB/GPIO1 pin function select: 000 = input (CSB / Jack detection: depending on MODE setting) 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1 3 GPIO1POL 0 GPIO1 Polarity invert 0 = Non inverted 1 = Inverted 6 GPIO1GPD 0 GPIO1 Internal pull-down enable: 0 = Internal pull-down disabled 1 = Internal pull-down enabled 7 GPIO1GPU 0 GPIO1 Internal pull-up enable: 0 = Internal pull-up disabled 1 = Internal pull-up enabled 8 GPIO1GP 0 GPIO1 Open drain enable 0 = Open drain disabled 1 = Open drain enabled R14(0Eh) 5:4 OPCLKDIV 00 PLL Output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 Table 45 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the GPIO1SEL[2:0] bits. Register R14(0Eh) bits [5:4] (OPCLKDIV) are used to control the PLL output clock division ratio and also the highpass filter cut-off in applications mode (HPFCUT). OPCLKDIV and HPFCUT cannot be set independently. |
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