công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

WM8946 bảng dữ liệu(PDF) 21 Page - Wolfson Microelectronics plc

tên linh kiện WM8946
Giải thích chi tiết về linh kiện  Stereo Low-Power CODEC with Video Buffer
PDF  175 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8946 bảng dữ liệu(HTML) 21 Page - Wolfson Microelectronics plc

Back Button WM8946 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 20Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 21Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 22Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 23Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 24Page - Wolfson Microelectronics plc WM8946 Datasheet HTML 25Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 175 page
background image
Production Data
WM8946
w
PD, July 2012, Rev 4.3
21
Figure 8 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)
Note: The data is latched on the 32
nd falling edge of SCLK after 32 bits have been clocked into the device.
SCLK
(input)
SDOUT
(output)
tDL
CS
(input)
Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)
Test Conditions
DCVDD = 1.8V, DBVDD = LDOVDD = SPKVDD = 3.3V, LDOVOUT = 3.0V, GND = 0V,
TA = +25
oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CS
¯¯ falling edge to SCLK rising edge
tCSU
40
ns
SCLK falling edge to CS rising edge
tCHO
10
ns
SCLK pulse cycle time
tSCY
200
ns
SCLK pulse width low
tSCL
80
ns
SCLK pulse width high
tSCH
80
ns
SDA to SCLK set-up time
tDSU
40
ns
SDA to SCLK hold time
tDHO
10
ns
Pulse width of spikes that will be suppressed
tps
0
5
ns
SCLK falling edge to SDOUT transition
tDL
40
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com