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CXP-85112 bảng dữ liệu(PDF) 10 Page - Sony Corporation

tên linh kiện CXP-85112
Giải thích chi tiết về linh kiện  CMOS 8-bit Single-chip Microcomputer
PDF  20 Pages
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nhà sản xuất  SONY [Sony Corporation]
Trang chủ  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXP-85112 bảng dữ liệu(HTML) 10 Page - Sony Corporation

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– 10 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
∗1 V
IN
and VOUT must not exceed VDD + 0.3V.
∗2 The high current operation transistor is the N-ch transistor of PD and PF0 to PF3.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions.
Exceeding these conditions may adversely affect the reliability of the LSI.
Supply voltage
Input voltage
Output voltage
Medium voltage drive output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
VIN
VOUT
VOUTP
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +7.0
–0.3 to +7.0∗1
–0.3 to +7.0∗1
–0.3 to +15.0
–5
–50
15
20
130
–20 to +75
–55 to +150
1000
600
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
mW
Pins PF0 to PF3
Total for all output pins
Excludes high current outputs
High current outputs∗2
Total for all output pins
SDIP
QFP
Symbol
Rating
Unit
Remarks
Absolute Maximum Ratings
(Vss = 0V reference)
Supply voltage
High level input voltage
Low level input voltage
Operating temperature
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
V
V
V
V
V
V
V
V
V
°C
Item
Symbol
Min.
Max.
Unit
Remarks
4.5
3.5
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–20
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
Guaranteed operation range
Low-speed mode guaranteed
operation range∗1
Guaranteed data hold range
during stop
Includes I2C Schmitt input∗2
CMOS Schmitt input∗3
EXTAL∗4
Includes I2C Schmitt input∗2
CMOS Schmitt input∗3
EXTAL∗4
VDD
∗1 Specifies only for 1/16 frequency demultiplication mode and sleep mode.
∗2 Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP.
∗3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC,
PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST.
∗4 Specifies only during external clock input.
Recommended Operating Conditions
(Vss = 0V reference)
Item



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