4256BWP datasheet(13/41 Pages) STMICROELECTRONICS

13 / 41 page

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF

Device operation

Doc ID 6757 Rev 28

13/41

4.5

Device addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 2(on Serial Data (SDA), most significant bit first).

When the device select code is received, the device only responds if the Chip Enable

Address is the same as the value on the Chip Enable (E2, E1, E0) inputs.

The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 2.

Device select code

Device type identifier(1)

The most significant bit, b7, is sent first.

Chip Enable address(2)(3)

E0, E1 and E2 are compared with the value read on input pins E0,E1,and E2.

For the 5-bump WLCSP package, (E0,E1,E2) inputs are internally connected to (0,0,1)

Device select code

when addressing the

memory array

1010

Device select code

when accessing the

Identification page

1011

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