CXP82940 datasheet(21/24 Pages) SONY

21 / 24 page

– 21 –

CXP82940/82948/82952/82960

(5) I2C bus timing

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus-free time before starting transfer

Hold time for starting transfer

Clock Low level width

Clock High level width

Setup time for repetitive transfers

Data hold time

Data setup time

SDA, SCL rise time

SDA, SCL fall time

Setup time for transfer completion

fSLC

tBUF

tHD; STA

tLOW

tHIGH

tSU; STA

tHD; DAT

tSU; DAT

tSU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

0∗

250

4.7

100

300

kHz

µs

Symbol

Condition

Min.

Max.

Unit

∗ The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.

Fig.10. I2C bus transfer timing

tSU ; STO

tSU ; STA

tHD ; STA

tSU ; DAT

tHIGH

tHD ; DAT

tLOW

tHD ; STA

tBUF

SDA

SCL

Fig.11. Recommended circuit example for I2C device

I2C

device

I2C

device

RS RS

RS RP

SDA0

(or SDA1)

SCL0

(or SCL1)

• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• Serial resistance (Rs = 300

Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by

CRT flash-over.

CXP82940 bảng dữ liệu(PDF) 21 Page - Sony Corporation

CXP82940 bảng dữ liệu(HTML) 21 Page - Sony Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL