SPEAR1310 datasheet(33/57 Pages) STMICROELECTRONICS

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SPEAr1310

TDM/E1 HDLC controller

Doc ID 17528 Rev 4

33/57

TDM/E1 HDLC controller

20.1

Main features

The main features of the TDM/E1 HDLC design are:

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AMBA 2.0 compliant

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AMBA slave interface, used to program TDM/E1

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AMBA master interface, used to transfer data between DDR and IP

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DMA engine included to alleviate CPU from transferring data

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Data buffer queue making bulk data transfer more efficient

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Interrupt Queue supplying more interrupt information

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Miscellaneous Interrupt generation

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Frame transmitted/received

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End of data buffer queue

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Buffer empty/ buffer filled

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Tx/Rx DMA FIFO underflow/overflow

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Interrupt queue overflow

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Interrupt FIFO overflow

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Abort generation and detection

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Oversize and non-octet-aligned frame detection

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CRC and alignment error generation

TDM interface features:

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Six signals

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Duplex Tx/Rx communication

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Up to 16 Mbps pre Tx/Rx channel

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256 time slots / frame(125 us)

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Supports any time-slot banding to any Tx/Rx channel

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Data sending/sampling time configurable

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Delay between bit 0 of TS0 and the SYNC signal configurable

E1 interface main features:

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Six signals

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Duplex Tx/Rx communication

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Up to 2 Mbps pre Tx/Rx channel

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32 time slot / frame(125 us)

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Supports any time-slot banding to any Tx/Rx channel

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Data sending/sampling time configurable

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Delay between the bit 0 of TS0 and the SYNC signal is configurable

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