SPIRIT1 datasheet(68/94 Pages) STMICROELECTRONICS

68 / 94 page

MCU interface

SPIRIT1

68/94

Doc ID 022758 Rev 3

10.2

Interrupts

In order to notify the MCU of a certain number of events an interrupt signal is generated on

a selectable GPIO. The following events trigger an interrupt to the MCU:

All interrupts are reported on a set of interrupt status registers and are individually

maskable. The interrupt status register must be cleared upon a read event from the MCU.

The status of all the interrupts is reported on the IRQ_STATUS[3:0] registers: bits are high

for the events that have generated any interrupts. The interrupts are individually maskable

Table 32.

Interrupts

Bit

Events group

Interrupt event

Packet oriented

RX data ready

RX data discarded (upon filtering)

2TX data sent

Max. re-TX reached

CRC error

TX FIFO underflow/overflow error

RX FIFO underflow/overflow error

TX FIFO almost full

TX FIFO almost empty

RX FIFO almost full

RX FIFO almost empty

Max. number of backoff during CCA

Signal quality related

Valid preamble detected

Sync word detected

RSSI above threshold (carrier sense)

Device status related

Wake-up timeout in LDCR mode(1)

The interrupt flag n.15 is set (and consequently the interrupt request) only when the XO clock is available

for the state machine. This time may be delayed compared to the actual timer expiration. However, the real

time event can be sensed putting the end-of-counting signal on a GPIO output.

READY(2)

The interrupt flag n.16 is set each time the SPIRIT1 goes to READY state and the XO has completed its

setting transient (XO ready condition detected).

STANDBY state switching in progress

Low battery level

Power-on reset

Brownout event

LOCK

Timer related

RX operation timeout

Others

AES end–of–operation

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