SPC564L54L5 datasheet(128/160 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC56XL60/54

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Doc ID 15457 Rev 8

3.19.4

Reset sequence — start condition

The impact of the voltage thresholds on the starting point of the internal reset sequence are

becoming important if the voltage rails / signals ramp up with a very slow slew rate

compared to the overall reset sequence duration.

Destructive reset

Figure 18 shows the voltage threshold that determines the start of the Destructive Reset

Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.

Figure 18. Reset sequence start for Destructive Resets

The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET

does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it

can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).

If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector

of the NVM.

If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow

sector of the NVM.

If RESET is configured for short reset

Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the

functional reset source which triggered the reset sequence.

Table 34.

Voltage Thresholds

Variable name

Value

Vmin

Refer to Table 19

Vmax

Refer to Table 19

Supply Rail

VDD_HV_PMU

TReset, max starts here

TReset, min starts here

Supply Rail

Vmax

Vmin

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