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SPC564L54L5 bảng dữ liệu(PDF) 124 Page - STMicroelectronics

tên linh kiện SPC564L54L5
Giải thích chi tiết về linh kiện  32-bit Power Architecture® microcontroller for automotive SIL3/ASILD chassis and safety applications
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SPC564L54L5 bảng dữ liệu(HTML) 124 Page - STMicroelectronics

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Electrical characteristics
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Doc ID 15457 Rev 8
Figure 12. Pad output delay
3.19
Reset sequence
This section shows the duration for different reset sequences. It describes the different reset
sequences and it specifies the start conditions and the end indication for the reset
sequences.
3.19.1
Reset sequence duration
Table 32 specifies the minimum and the maximum reset sequence duration for the five
different reset sequences described in Section 3.19.2, Reset sequence description.
VDDE/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
Table 32.
RESET sequences
No.
Symbol
Parameter
Conditions
TReset
Unit
Min
Typ
Max(1)
1TDRB
CC
Destructive Reset Sequence, BIST
enabled
40
47
51
ms
2TDR
CC
Destructive Reset Sequence, BIST
disabled
—
500
4200
5000
µs
3TERLB
CC
External Reset Sequence Long, BIST
enabled
41
45
49
ms
4TFRL
CC
Functional Reset Sequence Long
—
35
150
400
µs
5TFRS
CC
Functional Reset Sequence Short
—
1
4
10
µs
1.
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.



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