STA382BW datasheet(151/172 Pages) STMICROELECTRONICS

151 / 172 page

STA382BW

Doc ID 022783 Rev 1

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To be noted that once the check is performed, and the tristate released, the short protection

is not active anymore until the next EAPD 0->1 toggling which means that shorts that

happened during normal operation cannot be detected.

To be noted that register 0x47 is meaningful only after the EAPD bit is set to ‘1’ at least

once.

The short-circuit protections implemented are effective only in BTL configuration, and they

must not be activated if a single ended-application scheme is needed.

Figure 42.

Short-circuit detection timing diagram (no short detected)

In Figure 42 the short protection timing diagram is shown. The time information is expressed

in clock cycles, where the clock frequency is defined as in section 7.1.1. The gray color is

used for the SHOKx bits to indicate that the bits are carrying the status of the previous

EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD

transition occurs). GND-related SHOK bits are updated as soon as the gnd test is

completed, VCC bits are updated after the vcc test is completed, and the SOUT bit is

updated after the shorted output test is completed. The gnd test, vcc test and output test are

always run (if the SHEN bit active and EAPD is toggled to ‘1’), and only if both tests are

successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the

figure). If one of the three tests (or all) fail, the power bridge outputs are kept in tristate until

the procedure is restarted with a new EAPD toggling.

In this figure EAPD is intended to be bit 7 of register 0x05.

EAPD

OUT1A

OUT1B

OUT2A

OUT2B

SHOK1[7:4]

SHOK1[3:0]

SHOK2[0]

cycles

50005 cy c les

50005 cy cles

1c yc le

Start o ut test

TBD cycles

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