STA382BW datasheet(113/172 Pages) STMICROELECTRONICS

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STA382BW

Doc ID 022783 Rev 1

113/172

7.3

Configuration register C (addr 0x02)

7.3.1

FFX compensating pulse size register

Table 6:

7.4

Configuration register D (addr 0x03)

7.4.1

DSP bypass

Setting the DSPB bit bypasses the EQ function of the STA382BW.

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

Reserved

Table 113.

FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

Table 114.

Compensating pulse size

CSZ[3:0]

Compensating pulse size

0000

0 ns (0 ticks) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 ticks) clock period compensating pulse size

SME

ZDE

Reserved

BQL

PSL

DSPB

Reserved

Table 115.

DSP bypass

Bit

R/W

RST

Name

Description

R/W

DSPB

0: Normal operation

1: Bypass of biquad and bass/treble functions

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