STA350BW datasheet(78/86 Pages) STMICROELECTRONICS

78 / 86 page

STA350BW

78/86

Doc ID 018572 Rev 3

Two different behaviors can be configured by the VRESTG bit:

●

If VRESTG=’0’ the CxVR contribution will be applied immediately after the

corresponding I2C bits are written.

●

If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the

corresponding CxVol register or master volume register is written (even to the previous

values).

7.22

Quantization error noise correction (address 0x48)

A special feature inside the digital processing block is available. In case of poles positioned

at very low frequencies, biquad filters can generate some audible quantization noise or

unwanted DC level. In order to avoid this kind of effect, a quantization noise-shaping

capability can be used. The filter structure including this special feature, relative to each

biquad, is shown in Figure 32.

By default, this capability is not activated to maintain backward compatibility with all the

previous Sound Terminal products. The new feature can be enabled independently for each

biquad using the I2C registers. The D7 bit, when set, is responsible for activating this

function on the crossover filter while the other bits address any specific biquads according to

the previous table. Channels 1 and 2 share the same settings. Bit D7 is effective also for

channel 3 if the relative OCFG is used.

VRESEN

VRESTG

Mode

Extra Volume Resolution disabled

Volume fine-tuning enabled and applied immediately.

Volume fine-tuning enabled and applied when master or

channel volume is updated

NSHXEN

NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN NSHB1EN

00000000

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