STULPI01A_12 datasheet(35/44 Pages) STMICROELECTRONICS

35 / 44 page

STULPI01A, STULPI01B

ULPI registers

Doc ID 14817 Rev 4

35/44

Note:

0Dh-0Fh(Read), 0Dh(Write), 0Eh(Set), 0Fh(Clear).

If set, the bits in this register cause an interrupt event notification to be generated when the

corresponding PHY signal changes from low to high. By default, all transitions are enabled.

RxActive and RxError must always be communicated immediately and so are not included

in this register. Interrupt circuitry can be powered down in any mode when both rising and

falling edge enables are disabled. To ensure interrupts are detectable when clock is

powered down, the link should enable both rising and falling edges.

Table 20.

USB interrupt enable rising register

Field name

Bits

Access

Reset

Description

Host disconnect rise

rd/wr/s/c

Generates an interrupt event notification when host

disconnect changes from low to high. Applicable only in

Host mode (DpPulldown and DmPulldown both set to

1b).

VbusValid rise

rd/wr/s/c

Generates an interrupt event notification when

VbusValid changes from low to high.

SessValid rise

rd/wr/s/c

Generates an interrupt event notification when

SessValid changes from low to high. SessValid is the

same as UTMI+AValid.

SessEnd rise

rd/wr/s/c

Generates an interrupt event notification when SessEnd

changes from low to high.

ID rise

rd/wr/s/c

Generates an interrupt event notification when ID

changes from low to high. ID is valid 50 ms after

IdPullup is set to 1b, otherwise ID is undefined and

should be ignored.

Reserved

7:5

rd/wr/s/c

Reserved.

STULPI01A bảng dữ liệu(PDF) 35 Page - STMicroelectronics

STULPI01A bảng dữ liệu(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

bảng dữ liệu tải về

Link URL