STPM10 datasheet(27/51 Pages) STMICROELECTRONICS

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STPM10

Theory of operation

Doc ID 17728 Rev 3

27/51

7.16

Programming the STPM10

7.16.1

Data records

The STPM10 has 8 internal data record registers. Every data record consists of a 4-bit

parity code and 28-bit data value where the parity code is computed from the data value,

which makes a total of 32 bits, or 4 bytes.

Figure 21

shows the data record structure with the name of the contained information. Each

bit of parity nibble is defined as odd parity of all seven corresponding bits of data nibbles.

The first 6 registers are read-only, except for the 8-bit mode signals in the DFP register (the

mode signals are described later in this paragraph). The last two registers are CFL and

CFH.

7.17

Configuration bits

All the configuration bits that control the operation of the device (CFL and CFH data records)

can be written in a temporary way. The configuration bit values are written in the so-called

volatile memory, which are simple latches that hold the configuration data until the power is

on or until a reset condition occurs (both POR and remote reset).

As indicated in the data records table, the configuration bits are 56.

Figure 21.

STPM10 data records map

upper f(u)

0 1

mode signals

iRMS

uRMS

iMOM

uMOM

1bit

1bit 1bit

20 bit

8 bit

6 bit

11 bit

16 bit

DAP

DRP

DSP

CFH

DFP

DEV

DMV

CFL

reactive energy

type0 active energy

apparent energy

type 1 energy

lower part of configurators

upper part of configurators

Status

lower f(u)

parity

4 bit

msb

lsb

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