L6391 datasheet(11/21 Pages) STMICROELECTRONICS

11 / 21 page

L6391

Electrical characteristics

Doc ID 17892 Rev 1

11/21

Logic inputs

Vil

1, 2, 3

Low logic level voltage

0.8

Vih

High logic level voltage

2.25

Vil_S

1, 3

Single input voltage

LIN and HIN connected

together and floating

0.8

IHINh

HIN logic “1” input bias

current

HIN = 15 V

110

175

260

μA

IHINl

HIN logic “0” input bias

current

HIN = 0 V

μA

ILINl

LIN logic “0” input bias

current

LIN = 0 V

μA

ILINh

LIN logic “1” input bias

current

LIN = 15 V

μA

ISDh

SD logic “1” input bias

current

SD = 15 V

100

μA

ISDl

SD logic “0” input bias

current

SD = 0 V

μA

VBO = Vboot - Vout

RDSON is tested in the following way:

RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]

where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.

Table 8.

DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

Table 9.

Sense comparator (VCC = 15 V, TJ = +25 °C)

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Vio

8, 9

Input offset voltage

-15

Iib

8, 9

Input bias current

VCP+ = 1 V, VCP- = 0.5 V

μA

Vol

Open drain low level output

voltage

Iod = - 3 mA VCP+=1V;

VCP-=0.5V;

0.5

td_comp

Comparator delay

Rpull=100 kΩ to 5 V on

SD/OD pin; VCP-=0.5V;

voltage step on CP+ = 0 ÷

3.3V,

130

Slew rate

CL = 180 pF; Rpu = 5 kΩ

μs

L6391 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

L6391 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

bảng dữ liệu tải về

Link URL