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IS66WV51216DALL

IS66/67WV51216DBLL

Integrated Silicon Solution, Inc. — www.issi.com

1

Rev.  A

06/28/2011

8Mb LOW VOLTAGE, 

ULTRA LOW POWER PSEUDO CMOS STATIC RAM  

FEATURES

• High-speed access time:

– 70ns (IS66WV51216DALL, IS66/67WV51216DBLL)

– 55ns (IS66/67WV51216DBLL)

• CMOS low power operation

• Single power supply

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Lead-free available

DESCRIPTION

The

are high-speed, 8M bit static RAMs organized as 512K

words by 16 bits. It is fabricated using

performanceCMOStechnology.Thishighlyreliableprocess

coupled with innovative circuit design techniques, yields

high-performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW

(deselected) or when CS1 is LOW, CS2 is HIGH and both

LB

and UB are HIGH, the device assumes a standby mode

at which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE)

controls both writing and reading of the memory. A

data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

The IS66WV51216DALL and IS66/67WV51216DBLL are

packaged in the JEDEC standard 48-ball mini BGA (6mm

x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo

available for die sales.

FUNCTIONAL BLOCK DIAGRAM

JULY 2011

A0-A18

CS1

OE

WE

512K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

CS2