MSP430F2002IPWR datasheet(53/92 Pages) TI1

53 / 92 page

MSP430F20x3

MSP430F20x2

MSP430F20x1

www.ti.com

SLAS491H

– AUGUST 2005 – REVISED AUGUST 2011

Table 20. Port P1 (P1.4 to P1.7) Pin Functions, MSP430F20x1

CONTROL BITS / SIGNALS(2)

PIN NAME (P1.x)

FUNCTION(1)

P1DIR.x

P1SEL.x

CAPD.x

JTAG Mode

P1.4(3) input/output

0/1

N/A

P1.4/SMCLK/CA4/TCK

SMCLK

CA4(4)

TCK(5)

P1.5(3) input/output

0/1

N/A

P1.5/TA0/CA5/TMS

Timer_A2.TA0

CA5(4)

TMS(5)

P1.6(3) input/output

0/1

N/A

P1.6/TA1/CA6/TDI

Timer_A2.TA1

CA6(4)

TDI(5)

P1.7(3) input/output

0/1

N/A

P1.7/CAOUT/CA7/TDO/TDI

CAOUT

CA7(4)

TDO/TDI(5)(6)

(1)

N/A = Not available or not applicable

(2)

X = Don

't care

(3)

Default after reset (PUC/POR)

(4)

Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for

that pin, regardless of the state of the associated CAPD.x bit.

(5)

In JTAG mode the internal pullup/down resistors are disabled.

(6)

Function controlled by JTAG

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